1. Field of the Invention
The present invention relates to a method for forming semiconductor devices, and more particularly relates to a method for fabricating devices having an enhancement in high current drive capability and a diminishment in the area occupied by devices.
2. Description of the Prior Art
Given the present developments and changes in technology, integrated circuits (ICs) are gradually moving toward an ultra-high density target. Therefore, there is a trend toward the gradual diminishment in semiconductor device sizes and distances between devices. Thus, no matter how tiny devices integrated become, it is still very important to maintain the best operating condition within the devices. Conventional structures of high voltage CMOS (HV-CMOS) devices have channels and drift regions in the horizontal direction, which results in a larger chip area occupation. Therefore, a better and more advanced method for fabricating devices is needed urgently.
FIG. 1A shows a cross-sectional view of a structure of a conventional CMOS transistor. The structure comprises a p-type conductivity substrate 10, a N.sup.+ source electrode 11, a N.sup.+ drain electrode 12, a drift region 13, a field oxide (FOX) layer 14, a gate oxide layer 15, and a gate electrode 16.
In the structure of a conventional CMOS transistor described above, channel and drift regions are all the in horizontal direction and only source and drain electrode are located inside the substrate. This type of structure makes channel and drift regions of CMOS seems shorter in length. When the channel of CMOS device shrinks in length, hot carrier effects become more serious. There are many ways to solve hot carrier effects for short channel length CMOS devices. Wherein the simplest method is to reduce CMOS transistor's operating voltage. For example, 5V is reduced to 3.3V or even 2.5V, this reduces the channel's horizontal electric field and results in an ability to form any hot carrier. Although the phenomena of "carrier multiples" can be greatly reduced, the device would not be able to be used under high voltage operations. If it is desired to avoid reducing the operating voltage for CMOS transistors and also to solve hot carrier effects for short channel length CMOS devices, then the channel length of CMOS devices need to be increased. The structure in horizontal direction and an increase in the channel length would all occupy a greater chip area, which is against the trend of gradual diminishment of size in semiconductor devices.
Another method that is popular in solving hot carrier effects for short channel length CMOS devices is placing an N- type region with lower doping density at the place where the source/drain region draws near the channel. This kind of design has been called "Lightly Doped Drain", or LDD. The use of LDD is not a perfect solution. First of all, LDD makes CMOS fabrication more complicated. Next, due to the lower doping density of LDD, the series resistance between the source and drain would be higher. This causes a reduction in the device's operating speed and an increment in power dissipation.